The present invention relates to a processor and an instruction code generation device which generates an instruction code executable by the processor from a program described in a high level language. In particular, the present invention can be used suitably by a processor such as a microcomputer which has an instruction cache and prefetch function, and by a system using the processor.
In a processor including an instruction cache, the prefetch function is adopted widely, in order to prevent the degradation of processing capability due to a cache fill to be performed after a cache miss. The prefetch function predicts an instruction which the processor will execute in the future, and reads the instruction in advance to a prefetch buffer, such as an instruction cache, before a cache miss occurs. Various prefetch functions have been proposed, ranging from the simple prefetch function which reads an instruction at an address continuing the address of a currently executing instruction, to the high-performance prefetch function which is accompanied by branch prediction.
Patent Literature 1 discloses a processor which includes an FIFO (First-In First-Out) type prefetch buffer and which performs prefetching for every unit of instructions based on the word number of the instructions calculated by an instruction decoder. It is claimed that a system-wide bus efficiency can be enhanced by reducing the frequency of bus arbitration which takes place when an instruction is read into a prefetch buffer by the prefetch function.
(Patent Literature 1) Japanese Unexamined Patent Application Publication No. Hei 2 (1990)-242337